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LAYTOOLS
from Catena, Netherlands |
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LAYTOOLS are especially developed for
electronic layout design.
With its powerful multi-window all-angle IC
layout editor, the drawing of IC layouts is easy
and quickly mastered, even in the case of very
complex structures.
LAYTOOLS is available for PC-Windows, LINUX &
UNIX.
Furthermore our programme contains circuit
and power-electronics simulators. |
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| SPE : The Schematic
Editor |
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SPE is a
schematic capture package available for
MS-Windows platforms and offers designers a
more complete choice in affordable design
solutions. |
| Features |
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Schematic graphical data may be
created and processed in a hierarchically
structured form. |
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Data comprise of symbols, schematic
elements, attributes, text, buses, bus taps,
pins and wires (nets) connecting the used
components. |
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Symbols are the basic elements of a
schematic and represent primitive devices
(resistors, gates, etc.) or complex
sub-circuits (“BLOCK“ Symbols.) |
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Attributes describe characteristics or
properties of associated symbols, pins, or
nets. |
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Symbol files are usually contained in
library directories used for several
schematics. |
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SPE includes a NETLISTER for the output of
netlist files in several formats as XNDL,
SPICE, SMASH, SDL, VHDL, HILO, and EDIF used
for layout generation (place/route tools
like LAYPAR), for layout verification (e.g.
LAYVER), or for Simulation (e.g PSpice). |
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Crossprobing can be carried out together
with the tool LAYED when editing in SDLE
mode or viewing LAYVER evaluation results. |
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Schematic consistency checks can be carried
out. |
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Back annotation for simulation results.
Current version supports SMASH. |
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| LAYED : Layout Editor |
LAYED was
especially developed for electronic layout
design.
With the extensive LAYED command set, the
drawing of IC layouts is easy and quickly
mastered, even in the case of very complex
structures. These commands are available in
pull-down menus, through optional icons (the
tool box) and under short-cut keys. Direct
entry of the commands via the keyboard is
supported as well. |
| Advanced
Edit Features |
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Schematic
Netlist Driven Layout Editor (SDLE/NDLE) |
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Online DRC |
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Edit-in-place |
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Reference libraries |
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Any given scales and angles |
| Hierarchical data structures |
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256 Layers, 64
GDSII datatypes |
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Groups (cells or structures) |
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parametric groups (pGroups, pCells) |
| Evaluation
of LAYVER results |
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| LAYVER:
Layout Verification |
The Layout
Verification System LAYVER provides the user
with tools to:
Check an IC layout design with respect to
technological design rules (DRC).
Extract the realized (on chip) circuit and
compare it with the desired circuit (LVS).
Derive new layers by shrinking or bloating a
layer or perform logical operations on layers.
Calculate physical and electrical parameters
that depend on the geometry of drawn regions and
set minimum and maximum check limits to these
parameters for the LVS. |
| Design
Rule Check (DRC) |
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Huge set of
layer operations including logical, selectional
and sizing operations |
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Special DRC and edge operations |
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Error identification |
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Graphical evaluation with LAYED |
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flexibility of circuit extraction - no fixed technologies |
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Flexible
definition of devices to be extracted |
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User-defined expressions for parameter extraction |
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Parameter calculation |
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Parasitics extraction |
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User-defined parameter tolerances for comparison |
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Layout versus schematic comparison |
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Cross-probing |
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Schematic versus schematic comparison |
| Output
facilities |
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Output of
compressed vector files for LAYPLOT |
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Output of LAYVER results in the supported layout and netlist formats |
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| LAYPAR:
Place and Route |
| LAYPAR is a program for automatic
creation of standard cell arrays. LAYPAR
comprises the two main components LAYPLACE and
LAYROUTE as well as a dialog frame and
additional conversion tools. |
| LAYPLACE : Cell Placement |
| Features: |
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Generation of feed cell instances dependent on a given quota and deviation
mirroring of cells and cell rows working with user-controlled effort in
pre-, coarse and fine placement. |
| LAYROUTE : Auto Routing |
| Features: |
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Global routing based
on a user-defined grid feed through handling and
over cell routing 3-layer channel routing
generation of cell block layout in all supported
layout formats consideration of locked regions by
the routing process. |
| LAYPLOT: Layout Plot Program |
| LAYDRAC: Conversion Tool to
LAYVER |
| LAYCON: Conversion Tool CIF |
| LAYGERB: Conversion Tool GERBER |
| DBXMAN: Database Library Manager |
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| We are authorized and sole distributor for Catena range of products in Indian region. |
Catena Holding BV
Elektronicaweg 40
2628 XG Delft
The Netherlands
Tel: +31 15 275 6000
Fax: +31 15 275 6060
Email: info@catena.nl |
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