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MICROWIND 3 |
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Microwind, France, develops and markets electronic design software for designers of mixed-signal and analog IC, ASIC.
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MICROWIND3 is user friendly layout and simulation tool for sub-micron CMOS design. The MICROWIND3 allows the designer to simulate and design an integrated circuit at physical description level. The package contains a library of common logic and analog ICs to design and simulate. MICROWIND3 includes all the commands for a mask editor as well as verification tools never gathered before in a single module.
MICROWIND3 is truly a complete and cost-effective design solution for your CMOS design. |
| nanoLambda |
| VirtualFab |
| MEMsim |
| PROthumb |
| PROtutor |
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| DSCH Schematic editor and simulator |
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User-friendly environment for rapid design of logic circuits. |
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Handles both conventional pattern-based logic simulation and intuitive on-screen mouse-driven simulation. |
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Supports hierarchical logic design. |
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Built-in extractor which generates a SPICE netlist from the schematic diagram (Compatible with PSPICE™ and WinSpice™). |
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Current and power consumption analysis. |
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Generates a VERILOG description of the schematic for layout editor. |
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Immediate access to symbol properties (Delay, fanout). |
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Models and assembly support for 8051 and PIC 18f84. |
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Sub-micron, deep-submicron, nanoscale technology support. |
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Supported by huge symbol library. |
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| NanoLambda Precision CMOS Layout tool upto 35 nanometers. |
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Sub-micron, deep-submicron, nanoscale technology support. |
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Unsurpassed illustration capabilities. |
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Design-error-free cell library (Contacts, vias, MOS devices, etc..) |
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Advanced macro generator: capa, self, matrix, ROM, pads, path, etc..) |
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Incredible translator from logic expression into compact design-error free layout. |
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Powerful automatic compiler from VERILOG circuit into layout. |
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On-line design rule checker: width, spacing, overlap, extension rule verification. |
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Built-in extractor which generates a SPICE netlist from layout. |
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Extraction of all MOS width and length. |
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Parasitic capacitance, crosstalk and resistance extracted for all electrical nodes. |
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Import/Export CIF layout from 3rd party layout tools. |
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Up to 100,000 elementary boxes. |
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Lock & unlock layers to protect some part of the design from any changes. |
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Enhanced editing commands and layout control. |
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Support upto 8 metal layers for DSM
technologies.
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Global delay evaluation of circuit.
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Global cross talk analyzer.NEW |
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Inversion of diffusions boxes.
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Easy label listing.NEW |
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Enhanced mathematical signal
description.
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Zoom in navigator.
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Support till 22
nanometer technology.
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Enhanced memory utilization for
faster simulation.
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Silicon atom viewer.
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| PROthumb Mixed signal simulation and analysis |
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Built-in SPICE-like analog simulator features fast time-domain, voltage and current estimation, with very intuitive post processing: frequency estimation, delay estimation. (No external SPICE/ analog simulator.) |
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Supports LEVEL1, LEVEL3 and BSIM4 models for all technologies from 1.2µm downto 35nm |
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MOS characteristic viewer, with access to main model parameter. |
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Real-case measurement data-base in 0.7,0.35, 0.25 and 0.18µm for comparison with models. |
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The ability to label nodes allows intuitive control of the simulation (Supply, clock, pulse, PWL, sinus, maths) |
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Time-domain voltage and current waveforms available at the press of one single icon |
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DC/AC characteristics, signal frequency vs. time, eye diagrams |
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Min/Typ/Max analog simulation |
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Convenient Monte-carlo simulation |
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Powerful fast-Fourier Transform to support radio-frequency circuit simulation |
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On screen Power estimation |
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Sophisticated parametric simulation to investigate the effect of several key parameters on the circuit performances: R,L,C, temperature, supply voltage, etc. |
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Huge device simulation model library |
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Inbuild interconnect analyzer to compute field between ground planes and conductor |
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Enhanced memory utilization for faster
simulation.
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Onscreen storage of waveforms for result
hold-on.
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Now with forward & backward buttons to move in
simulation results.
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| VirtualFab Touch the deep-sub micron technology |
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3D fabrication process simulator with cross sectional viewer |
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Step-by-step 3-D visualization of fabrication for any portion of layout |
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See how the contacts and metallizations are created |
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See the self-aligned diffusion after the polysilicon gate is fabricated |
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Check planes of VDD, VSS, and others signals |
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Check the oxide structure, the low dielectric (Low K) and high K (SiO2) sandwich, and passivation |
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User can check the gate oxide and the MOS lateral drain diffusion structure
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Now 3D layout with GEL technology, where you
can rotate, move in-out through the layouts.
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| PROtutor Specially enabled university edition with enhanced training features |
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A valuable tutor to understand the MOS characteristics, with a user interface that beginners will like |
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Change the model parameters and see their effects on Id/Vd, Id/Vg Id(log)/Vg, threshold vs. Length |
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You can also fit the simulations with measurements we made in test-chips fabricated in 0.35, 0.25 and 0.18 mm |
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Full length tutorial on MOS models is provided in manual, with details on all parameters |
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Microwind3 supports models 1,3 and BSIM4 |
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200-pages documentation including several aspects of logic design |
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More than 150 basic circuits ready to simulate |
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| MEMsim Non volatile floating gate memory simulator |
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Simulation of non-volatile memories such as EPROM, EEPROM and FLASH using double-gate MOS. |
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Erasure of floating gates and removal all electrons. |
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Programming can be performed by a very high voltage supply on the gate. |
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The following technology library rules files are available along with detailed parameters for the Design Rule Checks (DRC Errors). |
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| Technology library available Minimum feature size |
Cmos12.rul 1.2um
Cmos08.rul 0.7um
Cmos06.rul 0.5um
Cmos035.rul 0.4um
Cmos025.rul 0.25um
Cmos018.rul 0.2um
Cmos012.rul 0.12um
Cmos90n.rul 0.1um
Cmos70n.rul 0.07um
Cmos50n.rul 0.05um |
| Note :
ni logic pvt. ltd. is authorized world wide distributor
& promoters from
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MICROWIND,
France, |
| www.microwind.net |
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